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quad , 12 - bit, 170 msps/210 msps serial output 1.8 v a d c data sheet ad9639 rev. b document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infri ngements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and regist ered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2009C 2013 analog devices, inc. all rights reserved. technical support www.analog.com features 4 adcs in one package jes d 204 c oded s erial digital outputs on - chip temp erature sensor ? 95 db channel - to - channel crosstalk snr: 65 dbfs with a in = 85 mhz at 210 msps sfdr: 77 dbc with ain = 85 mhz at 210 msps excellent linearity dnl: 0. 28 lsb (typ ical) inl: 0. 7 lsb (typical) 78 0 mhz full power analog bandwidth power dissipation : 3 25 mw per channel at 2 1 0 msps 1.25 v p- p input voltage range , adjustable up to 1.5 v p-p 1.8 v supply operation clock duty cycle stabilizer serial port interface features power - down modes digital test pattern enable programmable header programmable pin functions (pgmx, pdwn) applications communication receivers cable head end equipment/m - cmts broadband radios wireless infrastructure transceivers radar/military - aerospace s ubsystems test equipment functional block dia gram ad9639 12 channel d channel a channel b channel c vin + a dout + a dout ? a avdd pdwn drvdd drgnd 12 vin + b vin ? b dout + b dout ? b 12 vin + c dout + c dout ? c 12 vin ? a vcm a vcm b vin ? c vcm c sclk sdi/ sdio sdo csb vin + d vin ? d vcm d tempout dout + d dout ? d pgm3 pgm2 pgm1 pgm0 reset sha sha sha sha buf buf buf buf pipeline adc pipeline adc pipeline adc pipeline adc data serializer, encoder, and cml drivers serial port clk+ clk? data rate multiplier rbias reference 07973-001 figure 1. general description the ad9 6 39 is a quad, 12 - bit, 2 1 0 msps analog - to - digital con - verter (adc) with an on - chip temperature sensor and a high speed serial interface. it is designed to support the digitizing of high frequency, wide dynamic range signals with an input bandwidth of up to 780 mhz. the output data is serialized and presented in packet format , consisting of channel - specific information, coded samples , and error code correction. the adc requires a single 1.8 v power supply . t he input clock can be driven differential ly with a sine wave, lvpecl, cmos, or lvds . a clock duty cycle stabilizer allows high performance at full speed with a w ide range of clock duty c ycles. the on - chip reference eliminates the need for external decoupling and can be adjusted by means of spi control. var i ou s p owe r - down and standby modes are supported. the adc typically consumes 150 mw per channel with the digital link still in operation when standby operation is enabled. fabricated on an advanced cmos process, the ad9639 is avail - able in a pb - free/rohs - compliant, 72 - lead lfcsp package. it is specified over the industrial temperature range of ? 40 c to +85 c. product highlights 1. four adcs are contained in a small, space - saving package. 2. an on - chip pll allows users to provide a single adc sampling clock ; the pll distributes and multiplies up to produce the corresponding data rate clock. 3. the jesd 204 c oded data rate supports up to 4. 2 gbps per channel. 4. the ad9639 operates from a single 1.8 v power supply. 5. flexible synchronization schemes and programmable mode pins are available . 6. a n o n- chip temperature sensor is inclu ded .
ad9639 data sheet rev. b | page 2 of 36 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifica tions ..................................................................................... 3 ac specifications .......................................................................... 4 digital specifications ................................................................... 5 switching s pecifications .............................................................. 6 timing diagram ........................................................................... 7 absolute maximum ratings ............................................................ 8 ther mal resistance ...................................................................... 8 esd caution .................................................................................. 8 pin configuration and function descriptions ............................. 9 typical performance characteristics ........................................... 11 equivalent circuits ......................................................................... 15 theory of operation ...................................................................... 17 analog input considerations ................................................... 17 clock input considerations ...................................................... 19 digital outputs ........................................................................... 21 serial port interface (spi) .............................................................. 29 hardware interface ..................................................................... 29 memory map .................................................................................. 31 reading the memory map table .............................................. 31 reserved locations .................................................................... 31 default values ............................................................................. 31 logic levels ................................................................................. 31 applications information .............................................................. 35 power and ground recomm endations ................................... 35 exposed paddle thermal heat slug recommendations ...... 35 outline dimensions ....................................................................... 36 ordering guide .......................................................................... 36 revision history 7 /13 rev. a to rev. b change to current drive parameter, table 1 ................................ 3 updated outline dimensions ....................................................... 36 2/10 rev . 0 to rev. a changes to differential input voltage range parameter, table 1 ................................................................................................ 3 changes to table 7 ............................................................................ 9 changes to digital outputs and timing section ....................... 25 change to addr. (hex) 0x01, table 15 ......................................... 32 5/0 9 revision 0: initial version
data sheet ad9639 rev. b | page 3 of 36 specifications avdd = 1.8 v, drvdd = 1.8 v , t min = ? 40 c, t max = +85 c, 1.25 v p - p diffe rential input , ain = ?1.0 dbfs, dcs enabled, unless otherwise noted. table 1. ad9639bcpz - 170 ad9639bcpz - 210 parameter 1 temp min typ max min typ max unit resolution 12 12 bits accuracy no missing codes full guar anteed guaranteed offset error 25c ?2 12 ?2 12 mv offset matching 25c 4 12 4 12 mv gain error 25c ?2.8 +1 +4.7 ?2.8 +1 +4.7 % fs gain matching 25c 0.9 2.7 0.9 2.7 % fs differential nonlinearity (dnl) full 0.28 0.6 0.28 0.6 lsb inte gral nonlinearity (inl) full 0.45 0.9 0.7 1.3 lsb analog inputs differential input voltage range 2 full 1.0 1.25 1.5 1.0 1.25 1.5 v p -p common - mode voltage full 1.4 1.4 v input capacitance 25c 2 2 pf input resistance full 4.3 4.3 k? analog bandwidth, full power full 780 780 mhz voltage common mode ( vcm x pins ) voltage output full 1.4 1.44 1.5 1.4 1.44 1.5 v current drive full 1 1 ma temperature sensor output ?1.12 ?1.12 mv/ c voltage output full 739 737 mv current drive full 50 50 a power supply avdd full 1.7 1.8 1.9 1.7 1.8 1.9 v drvdd full 1.7 1.8 1.9 1.7 1.8 1.9 v i avdd full 535 570 610 650 ma i drvdd full 98 105 111 120 ma total power dissipation (including output drivers) f ull 1.139 1.215 1.298 1.386 w power - down dissipation full 3 3 mw standby dissipation 2 full 152 173 mw crosstalk full ?95 ?95 db overrange condition 3 full ?90 ?90 db 1 see the an - 835 application note , understanding high speed adc testing and evaluation , for definitions and details on how these t est s were completed. 2 avdd/drvdd, with link established. 3 overr ange condition is specified as 6 db above the full - scale input range.
ad9639 data sheet rev. b | page 4 of 36 ac specifications avdd = 1.8 v, drvdd = 1.8 v, t min = ? 40 c, t max = +85 c, 1.25 v p - p differential input, ain = ? 1.0 dbfs, dcs enabled, unless otherwise noted. table 2. ad9639 bcpz - 170 ad9639 bcpz - 210 parameter 1 temp min typ max min typ max unit signal - to - noise ratio (snr) f in = 84.3 mhz full 63.5 64.5 63.2 64.2 db f in = 240.3 mhz 25c 64.1 63.2 db signal - to - (noise + distortion) (sinad) ratio f in = 84.3 mhz full 63.3 64.4 62.8 63.9 db f in = 240.3 mhz 25c 63.9 63 db effective number of bits (enob) f in = 84.3 mhz full 10.2 10.4 10.1 10.3 bits f in = 240.3 mhz 25c 10.3 10.2 bits worst harmonic ( second ) f in = 84.3 mhz full 87.5 78.6 86 77 dbc f in = 240.3 mhz 25c 82 80 dbc worst harmonic (third) f in = 84.3 mhz full 79 74 76 72.6 dbc f in = 240.3 mhz 25c 84 77 dbc worst other (excluding second or third) f in = 84.3 mhz full 96 86 90 83.7 dbc f in = 240.3 mhz 25c 88 88 dbc two - tone intermod ulation distortion (imd) f in1 = 140.2 mhz, f in2 = 141.3 mhz, ain1 an d ain2 = ?7.0 dbfs 25c 78 77 dbc f in1 = 170.2 mhz, f in2 = 171.3 mhz, ain1 and ain2 = ?7.0 dbfs 2 25c 77 dbc 1 see the an - 835 application note , understanding high speed adc testing and evaluation , f or definitions and d etails on how these t est s were completed. 2 tested at 170 msps and 210 msps.
data sheet ad9639 rev. b | page 5 of 36 digital specificatio ns avdd = 1.8 v, drvdd = 1.8 v, t min = ? 40 c, t max = +85 c, 1.25 v p - p differential input, ain = ? 1.0 dbfs, dcs enabled, unless otherwise noted. table 3. ad9639bcpz - 170 ad9639bcpz - 210 parameter 1 temp min typ max min typ max unit clock inputs (clk+, clk ?) logic compliance full lvpecl/lvds/cmos lvpecl/lvds/cmos differential in put voltage full 0.2 6 0.2 6 v p -p input voltage range full avdd ? 0.3 avdd + 1.6 avdd ? 0.3 avdd + 1.6 internal common - mode bias full 1.2 1.2 v input common - mode voltage full 1.1 avdd 1.1 avdd v high level input voltage (v ih ) full 1.2 3.6 1.2 3.6 v low level input voltage (v il ) full 0 0.8 0 0.8 v high level input current ( i ih ) full ?10 +10 ?10 +10 a low level input current (i il ) full ?10 +10 ?10 +10 a differential input resistance 25c 16 20 24 16 20 24 k? input capacitance 25c 4 4 pf logic inputs (pdwn, csb , sdi/sdio, sclk, reset, pgmx) 2 logic 1 voltage full 0.8 avdd 0.8 avdd v logic 0 voltage full 0.2 avdd 0.2 avdd v logic 1 input current (csb) full 0 0 a logic 0 input current (csb) full ?60 ?60 a logic 1 input current (pdwn, sdi/sdio, sclk, reset, pgmx) full 55 55 a logic 0 input current (pdwn, sdi/sdio, sclk, reset, pgmx) full 0 0 a input resistance 25c 30 30 k? input capacitance 25c 4 4 pf logic output (sd o) logic 1 voltage full 1.2 avdd + 0.3 1.2 avdd + 0.3 v logic 0 voltage full 0 0.3 0 0.3 v digital outputs (dout + x, dout ? x) logic compliance cml cml differential output voltage full 0.8 0.8 v common - mode voltage ful l drvdd/2 drvdd/2 v 1 see the an - 835 application note , understanding high speed adc testing and evaluation , f or definitions and details on how these t est s were completed. 2 specified for 13 sdi/sdio pins on the same spi bus.
ad9639 data sheet rev. b | page 6 of 36 switching specificat ions avdd = 1.8 v, drvdd = 1.8 v, t min = ? 40 c, t max = +85 c, 1.25 v p - p differential input, ain = ? 1.0 dbfs, dcs enabled, unless otherwise noted. table 4. ad9639bcpz - 170 ad9639bcp z- 210 parameter 1 temp min typ max min typ max unit clock clock rate full 100 170 100 210 msps clock pulse width high (t eh ) full 2.65 2.9 2.15 2.4 ns clock pulse width low (t el ) full 2.65 2.9 2.15 2.4 ns data output parameters data output period or ui (dout + x, dout ? x) full 1/( 20 f clk ) 1/( 20 f clk ) seconds data output duty cycle 25c 50 50 % data valid time 25c 0.8 0.8 ui pll lock time (t lock ) 25c 4 4 s wake - up time (standby) 25c 250 250 ns wake - up time (power - down) 2 25c 50 5 0 s pipeline latency full 40 40 clk cycles data rate per channel (nrz) 25c 3.4 4.2 gbps deterministic jitter 25c 10 10 ps random jitter 25c 6 6 ps rms channel -to - channel bit skew 25c 0 0 seconds channel -to - channel packet ske w 3 25c 1 1 clk cycles output rise/fall time 25c 50 50 ps termination characteristics differential termination resistance 25c 100 100 ? aperture aperture delay (t a ) 25 c 1.2 1.2 ns aperture uncertainty (jitter) 25c 0.2 0.2 ps rms out - of - range recovery time 25c 1 1 clk cycles 1 see the an - 835 application note , understanding high speed adc testing and evaluation , f or definitions and details on how these t est s were completed. 2 receiver dependent. 3 see the serial data frame sec tion.
data sheet ad9639 rev. b | page 7 of 36 timing diagram ... ... ... ... ... ... ... ... sample n serial coded samples: n ? 40, n ? 39, n ? 38, n ? 37 ... n ? 39 n ? 40 n ? 38 n ? 37 n + 1 analog input signa l sample rate clock sample rate clock serial data output 07973-002 figure 2. timing diagram
ad9639 data sheet rev. b | page 8 of 36 absolute maximum rat ings table 5. parameter rating avdd to agnd ? 0.3 v to +2.0 v dr vdd to drgnd ?0.3 v to +2.0 v agnd to drgnd ?0.3 v to +0.3 v avdd to drvdd ?2.0 v to +2.0 v dout + x /dout ? x to drgnd ?0.3 v to drvdd + 0.3 v sdo, sdi/sdio , clk, vin x, vcm x, tempout, rbias to agnd ?0.3 v to avdd + 0.3 v sclk, csb, pgmx, reset, p dwn to agnd ?0.3 v to avdd + 0.3 v storage temperature range ?65c to +125c operating temperature range ?40c to +85c lead temperature (soldering , 10 sec) 300c junction temperature 150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress ra t ing only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to abs o lute maximum rating conditions for extended periods may affect device reliability. thermal resistance the exposed paddle must be soldered to the ground plane for the lfcsp package. soldering the expos ed paddle to the printed circuit board ( pcb) increases the reliabilit y of the solder joints, maximizing the the r mal capability of the package. table 6 . thermal resistance package type ja jb jc unit 72- lead lfcsp (cp -72-3) 16.2 7.9 0.6 c/w typical ja , jb , and jc values are specified for a 4 - layer board in still air. airflow increases heat dissipation, effectively reducing ja . in addition, metal in direct contact with the package leads from metal traces , through holes, ground, and power planes re duces ja . esd caution
data sheet ad9639 rev. b | page 9 of 36 pin configuratio n and function descr iption s 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 nc tempout rbias avdd nc nc avdd vcm d avdd vin ? d vin + d avdd avdd avdd avdd clk? 17clk+ 18avdd 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 nc avdd avdd reset drgnd drvdd dout + d dout ? d dout + c dout ? c dout + b dout ? b dout + a dout ? a drvdd drgnd 35 pdwn 36nc 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 nc pgm0 pgm1 pgm2 pgm3 nc avdd vcm a avdd vin ? a vin + a avdd avdd avdd csb sclk sdi/sdio sdo 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 nc avdd vcm c avdd vin ? c vin + c avdd avdd avdd nc avdd avdd avdd vin + b vin ? b avdd vcm b avdd pin 1 indicator ad9639 top view (not to scale) pin 0 = epad = agnd notes 1. nc = no connect. 2. the exposed paddle must be soldered to the ground plane for the lfcsp package. soldering the exposed paddle to the pcb increases the reliability of the solder joints, maximizing the thermal capability of the package. 07973-004 figure 3 . pin configuration table 7 . pin function descriptions pin no. mnemonic description 0 agnd analog ground (exposed paddle) . the exposed paddle must be soldered to the ground plane. soldering the exposed paddle to the pcb increases the reliability of the solder joints, maximizing the thermal capability of the package. 1, 5, 6, 19, 36, 49, 54, 63, 72 nc no connection. 2 tempout output voltage to monitor temperature . 3 rbias external resistor to set the internal adc core bias current. 4, 7, 9, 12, 13, 14, 15, 18, 20, 21, 41, 42, 43, 46, 48, 55, 57, 60, 61, 62, 64, 65, 66, 69, 71 avdd 1.8 v analog supply. 8 vcm d common - mode output voltage reference . 10 vin ? d adc d analog input complement . 11 vin + d adc d analog input true . 16 clk? clock input complement . 17 clk+ clock input true . 22 reset reset enable pin. resets the digital output t iming . 23, 34 drgnd digital output driver ground. 24, 33 drvdd 1.8 v digital output driver supply. 25 dout + d adc d digital output true . 26 dout ? d adc d digital output complement . 27 dout + c adc c digital output true . 28 dout ? c adc c digital output complement . 29 dout + b adc b digital output true . 30 dout ? b adc b di gital output complement .
ad9639 data sheet rev. b | page 10 of 36 pin no. mnemonic description 31 dout + a adc a digital output true . 32 dout ? a adc a digital output complement . 35 pdwn power - down . 37 sdo serial data output for 4-w ire spi i nterface. 38 sdi/sdio serial data input/ serial data i nput/output for 3 - wire spi interface . 39 sclk serial clock . 40 csb chip select bar . 44 vin + a adc a analog input true . 45 vin ? a adc a analog input complement . 47 vcm a common - mode output voltage reference . 50 , 51, 52, 53 pgm3 , pgm2, pgm1, pgm0 optional pin s to be programmed by customer. 56 vcm b common - mode output voltage reference . 58 vin ? b adc b analog input complement . 59 vin + b adc b analog input true . 67 vin + c adc c analog input true . 68 vin ? c adc c analog input complement . 70 vcm c common - mode output volta ge reference .
data sheet ad9639 rev. b | page 11 of 36 typical performance characteristics 0 ?20 ?40 ?60 ?80 ?100 ?120 0 10 20 30 40 50 60 70 80 frequency (mhz) amplitude (dbfs) ain = ?1.0dbfs snr = 64.88db enob = 10.49 bits sfdr = 77.57dbc 07973-059 figure 4 . single - tone 32k fft with f in = 84 .3 mhz, f sample = 170 msps 0 ?20 ?40 ?60 ?80 ?100 ?120 0 10 20 30 40 50 60 70 80 frequency (mhz) amplitude (dbfs) ain = ?1.0dbfs snr = 63.95db enob = 10.33 bits sfdr = 78.90dbc 07973-060 figure 5 . single - tone 32k fft with f in = 240.3 mhz, f sample = 170 msps 0 ?20 ?40 ?60 ?80 ?100 ?120 0 20 40 60 80 100 frequency (mhz) amplitude (dbfs) ain = ?1.0dbfs snr = 64.65db enob = 10.44 bits sfdr = 77.54dbc 07973-061 figure 6 . single - tone 32k fft with f in = 84 .3 mhz, f sample = 210 msps 0 ?20 ?40 ?60 ?80 ?100 ?120 0 20 40 60 80 100 frequency (mhz) amplitude (dbfs) ain = ?1.0dbfs snr = 63.13db enob = 10.19 bits sfdr = 76.07dbc 07973-062 figure 7 . single - tone 32k fft with f in = 240.3 mhz, f sample = 210 msps 70 69 68 67 66 65 64 63 62 61 60 50 70 90 110 130 150 170 190 210 230 250 encode (msps) snr (dbfs) 210msps 170msps 07973-067 figure 8 . snr vs. encode, f in = 84 .3 mhz 90 88 86 84 82 80 78 76 74 72 70 50 70 90 110 130 150 170 190 210 230 250 encode (msps) sfdr (dbfs) 210msps 170msps 07973-068 figure 9 . sfdr vs. encode, f in = 8 4.3 mhz
ad9639 data sheet rev. b | page 12 of 36 100 90 80 70 60 50 40 30 20 10 0 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 analog input level (dbfs) snr/sfdr (db) sfdr (dbfs) sfdr (db) snr (dbfs) snr (db) 07973-069 figure 10 . snr /sfdr vs. analog input level, f in = 84 .3 mhz , f sample = 170 msps 100 90 80 70 60 50 40 30 20 10 0 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 analog input level (dbfs) snr/sfdr (db) sfdr (dbfs) sfdr (db) snr (dbfs) snr (db) 07973-070 figure 11 . snr/ sfdr vs. analog input level, f in = 8 4.3 mhz , f sample = 210 msps 0 ?20 ?40 ?60 ?80 ?100 ?120 0 10 20 30 40 50 60 70 80 frequency (mhz) amplitude (dbfs) ain1 and ain2 = ?7.0dbfs sfdr = 77.26dbc imd2 = ?86.55dbc imd3 = ?77.26dbc 07973-072 figure 12 . two - tone 32k fft with f in1 = 1 40.2 mhz and f in2 = 1 41.3 mhz, f sample = 17 0 msps 0 ?20 ?40 ?60 ?80 ?100 ?120 0 20 40 60 80 100 frequency (mhz) amplitude (dbfs) ain1 and ain2 = ?7.0dbfs sfdr = 75.44dbc imd2 = ?78.34dbc imd3 = ?75.44dbc 07973-073 figure 13 . two - tone 32k fft with f in1 = 140.2 mhz and f in2 = 1 41.3 mhz, f sample = 210 msps 0 ?20 ?40 ?60 ?80 ?100 ?120 0 20 40 60 80 100 frequency (mhz) amplitude (dbfs) ain1 and ain2 = ?7.0dbfs sfdr = 76.88dbc imd2 = ?78.75dbc imd3 = ?78.68dbc 07973-074 figure 14 . two - tone 32k fft with f in1 = 170.2 mhz and f in2 = 171.3 mhz, f sample = 21 0 msps 95 90 85 80 75 70 65 60 55 50 45 0 50 100 150 200 250 300 350 400 450 500 ain frequency (mhz) amplitude (dbfs) sfdr (db) snr (db) 07973-077 figure 15 . snr/sfdr amplitude vs. ain frequency, f sample = 17 0 msps
data sheet ad9639 rev. b | page 13 of 36 95 90 85 80 75 70 65 60 55 50 45 0 50 100 150 200 250 300 350 400 450 500 ain frequency (mhz) amplitude (dbfs) sfdr (db) snr (db) 07973-078 figur e 16 . snr/sfdr amplitude vs. ain frequency, f sample = 210 msps 70 69 68 67 66 65 64 63 62 61 60 ?40 ?20 0 20 40 60 80 temperature (c) snr (db) snr, 210msps snr, 170msps 07973-080 figure 17 . snr vs. temperature, f in = 84 .3 mhz 90 85 80 75 70 65 60 ?40 ?20 0 20 40 60 80 temperature (c) sfdr (db) sfdr, 210msps sfdr, 170msps 07973-081 figure 18 . sfdr vs. temperature, f in = 84.3 mhz 0.8 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0 4500 4000 3500 3000 2500 2000 1500 1000 500 code inl (lsb) 07973-119 figure 19 . inl, f in = 9.7 mhz, f sample = 21 0 msps 0.4 ?1.2 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0 4500 4000 3500 3000 2500 2000 1500 1000 500 code dnl (lsb) 07973-120 figure 20 . dnl, f in = 9.7 mhz, f sample = 2 1 0 msps 40,000 35,000 30,000 25,000 20,000 15,000 10,000 5000 0 n ? 3 n ? 2 n ? 1 n n + 1 n + 2 n + 3 more number of hits bin input referred noise: 0.72 lsb 07973-106 figure 21 . input - referred noise histogram, f sample = 170 msps
ad9639 data sheet rev. b | page 14 of 36 40,000 35,000 30,000 25,000 20,000 15,000 10,000 5000 0 n ? 3 n ? 2 n ? 1 n n + 1 n + 2 n + 3 more number of hits bin input referred noise: 0.70 lsb 07973-107 figure 22 . input - referred noise histogram, f sample = 2 1 0 msps 0 ?120 ?100 ?80 ?60 ?40 ?20 0 120 100 80 60 40 20 frequency (hz) amplitude (dbfs) 07973-123 figure 23 . noise power ratio (npr) , f sample = 21 0 msps 90 40 45 50 55 60 65 70 75 80 85 1.0 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 analog input common-mode voltage (v) snr/sfdr (db) 07973-124 snr sfdr figure 24 . snr/sfdr vs. analog input common - mode voltage, f in = 84.3 mhz, f sample = 2 1 0 msps 0 ?25 ?20 ?15 ?10 ?5 1m 1g 100m 10m ain frequency (hz) amplitude (dbfs) 07973-125 figure 25 . full - power bandwidth amplitude vs. ain frequency, f sample = 2 1 0 msps
data sheet ad9639 rev. b | page 15 of 36 equivalent circuits 1.2v 10k? 10k? clk+ clk? avdd 07973-005 figure 26 . clk inputs vin + x avdd buf vin ? x avdd buf 2k? 2k? buf avdd ~1.4v 07973-006 figure 27 . analog i nputs sclk, pdwn, pgmx, reset 175 ? 30k ? 07973-007 figure 28 . equivalent sclk, reset, pdwn, pgmx input circuit csb 1k ? 26k ? avdd 07973-008 figure 29 . equivalent csb input circuit sdi/sdio 250? avdd avdd 30k ? 07973-009 figure 30 . equivalent sdi/sdio input circuit a vdd tempout 07973-010 figure 31 . equivalent tempout output circuit 175? 100? rbias 07973-011 figure 32 . equivalent rbias input/output circuit 175? vcm x 07973-012 figure 33 . equivalent vcm x output circuit
ad9639 data sheet rev. b | page 16 of 36 v cm dr vdd dout + x dout ? x 4m a 4m a 4m a 4m a r term 07973-089 figure 34 . equivalent digital output circuit a vdd a vdd 345? sdo 07973-030 figure 35 . equivalent sdo output circuit
data sheet ad9639 rev. b | page 17 of 36 theory of operation the ad9639 architecture consists of a differential input buffer and a front - end sample - and - hold amplifier (sha) followed by a pipe - lined switched - capac i tor adc. the quantized outputs from each stage are combined into a final 12 - bit result in the digital correction logic. the pipelined architecture pe r mits the first stage to operate on a new input sample while the remaining stages operate o n pre - ceding samples. sampling o c curs on the rising edge of the clock. each stage of the pipeline, excluding the last, consists of a low resolution fl ash adc connected to a switched - capacitor dac and interstage residue amplifier ( for example, a multiplying digital - to - analog converter ( mdac ) ). the residue amplifier magnifies the difference between the reconstructed dac output and the flash input for the next stage in the pipeline. one bit of redundancy is used in each stage to facilitate digital correction o f flash errors. the last stage si m ply consists of a flash adc. the input stage contains a differential sha that can be ac - or dc - coupled in diff erential or single - ended mode. the output of the pipeline adc is put into its final serial format by the data se rializer, encoder, and cml drivers block. the data rate multiplier creates the clock used to output the high speed serial data at the cml outputs. analog input considerations the analog input to the ad9639 is a differential buffer. this input is optimized to provide superior wideband performance and requires that the analog inputs be driven differentially. snr and sinad performance degrades if the analog input is driven with a single - ended signal. for best dynamic performance, the source impedances driving vin + x and vin ? x should be matched such that common - mode settling errors are symmetrical. these errors are reduced by the common - mode rejection of the adc. a small resistor in s eries with each input can help to r educe the peak transient current injecte d from the output st age of the driving source. in addition, low q inductors or ferrite beads can be placed on each leg of the input to reduce high differential capacitance at the analog inputs and , therefore , achieve the maximum band - width of the adc. the use of low q inductors or ferrite beads is required when driving the converter front end at high if frequencies. either a shunt capacitor or two single - ended capacitors can be placed on the inputs to provide a matching passive network. this ultimately crea tes a low - pass filter at the input to limit unwanted broadband noise. see the an - 827 application note and the analog dialogue article transfor mer - coupled front - end for wideband a/d converters (volume 39, number 2, april 2005) for more information on this subject. in general, the precise values depend on the appl ication. maximum snr performance is achieved by setting the adc to the largest span in a differential configuration. in the case of the ad9639 , the default input span is 1.25 v p-p. to configure the adc for a different input span , see the v ref regi ster ( ad dress 0x 18) . for the best performance , an input span of 1.25 v p- p or greater should be used (s ee table 15 for details ). differential input configurations t he ad9639 can be driven actively or passively; in either case , optimum performance is achieved by driving the analog input differentially. for example, using the ada4937 differential ampli - fier to drive the ad9639 provides excellent performance and a flexible interface to the adc fo r baseband and second nyquist (~100 mhz if) applications (see figure 36 and figure 37 ) . in either application , use 1% resistors for good gain matching. note that the dc - cou pled configuration show s some degradation in spurious per - formance . for more information , consult the ada4937 data sheet. signal generator +v s ?v s 3.3v 205? 205? 200? 200? 10k? 62? 10k? 27? 0.1f 1.25v p-p ada4937 g = unity vin + x vin ? x optional c 33? 33? 24? 24? 0.1f 0.1f r c avdd drvdd 1.8v 1.8v ad9639 adc input impedance 1.65v v ocm 07973-090 figure 36 . differential amplifier configuration for ac - cou pled baseband applications signal generator +v s ?v s 3.3v 205? 205? 200? 200? 62? 27? 0.1f 1.25v p-p ada4937 g = unity vin + x vin ? x optional c 33? 33? 24? 24? r c avdd drvdd 1.8v 1.8v ad9639 adc input impedance v ocm vcm x 1.4v 07973-091 figure 37 . differ ential amplifier configuration for dc - coupled baseband applications
ad9639 data sheet rev. b | page 18 of 36 for applications where snr is a key parameter, differential transformer coupling is the recom mended input configura tion to achieve the true performance of the ad9639 (see figure 38 to figure 40 ). regardless of the configuration, the value of the shunt capacitor, c, is dependent on the input frequency and may need to be reduced or removed. *c diff is optional 1.25v p-p 33? 33? *c diff c 50 0.1f a gnd adt1-1wt 1:1 z ratio vin ? x adc ad9639 vin + x c 0.1f 07973-013 figure 38 . differential transformer - coupled configuration for baseband applications adc ad9639 1.25v p-p 2.2pf 0.1f adt1-1wt 1:1 z ratio l l 0.1f l 33 ? 33 ? 250 ? 65 ? vin + x vin ? x 07973-014 figure 39 . differential transformer - coupled configuration for wideband if applications adc ad9639 1.25v p-p l 0.1f adt1-1wt 1:1 z ratio 0.1f 33 ? 33 ? 250 ? vin + x vin ? x 07973-015 fig ure 40 . differential transformer - coupled configuration for narrow - band if applications 1.25v p-p 33 ? 33 ? 0.1f 0.1f 66 vin ? x adc ad9639 vin + x 4.7pf 0.1f balun 1:1 z balun 1:1 z 07973-017 figure 41 . differential balun - coupled configuration for wideband if applications single - ended input configuration a single - ended input may provide adequate performance in cost - sensitive applications. in this configuration, sfdr and distortion performance can degrade due to input common - mode swing mismatch . if the application requires a single - ended input configuration , ensure that the source impedances on each input are well matched to achieve the best possible perf ormance. a full - scale input of 1.25 v p - p can be applied to the vin + x pin of the ad 9639 while the vin ? x pin is terminated. figure 42 show s a typical single - ended input configuration. 1.25v p-p 33 ? 33 ? 49.9 0.1f 0.1f 25 vin ? x adc ad9639 vin + x *c diff c *c diff is optional c 07973-016 figure 42 . single - ended input configuration
data sheet ad9639 rev. b | page 19 of 36 clock input considerations for optimum performance, the ad9639 sample clock inputs (clk+ and clk?) should be clocked with a differential signal. this signal is typically ac - coupled to the clk+ and clk? pins via a transformer or capacitors. these pins are biased internally to 1.2 v and require no add i tional biasing. fi gure 43 shows a preferred method for clocking the ad9639 . the low jitter cl ock source is converted from a single - ended signal to a differential signal using an rf transformer. the back - to - back schottky diodes across the secondary transformer limit clock e xcursions into the ad9639 to approximately 0.8 v p - p diffe r ential. this helps to prevent the large voltage swings of the clock from feeding through to other portions of the ad9639 , and it preserves the fast rise and fall times of the signal, which are crit ical to low jitter performance. 0.1f 0.1f 0.1f 0.1f schottky diodes: hsms-2812 clk+ 50? clk? clk+ adt1-1wt, 1:1z xfmr adc ad9639 07973-018 figure 43 . transformer - coupled differential clock another option is to ac - couple a differential pecl signal to the sample clock input pins as shown in figure 44 . the ad9510 / ad9511 / ad9512 / ad9513 / ad9514 / ad9515 / ad9516 / ad9518 family of clock drivers o f fers excellent jitter performance. 10 0? 0.1f 0.1f 0.1f 0.1f 240 ? 240 ? 50 ?* 50 ?* clk clk clk? clk+ adc ad9639 pecl driver clk+ clk? ad9510/ad9511/ ad9512/ad9513/ ad9514/ad9515/ ad9516/ad9518 *50? resistors are optional. 07973-019 figure 44 . differential pecl sample clock 10 0? 0.1f 0.1f 0.1f 0.1f 50?* 50?* clk clk clk? clk+ adc ad9639 lvds driver clk+ clk? ad9510/ad9511/ ad9512/ad9513/ ad9514/ad9515/ ad9516/ad9518 *50? resistors are optional. 07973-020 figure 45 . differential lvds sample clock in some applications, it is acceptable to drive the sample clock inputs with a single - ended cmos signal. in such applications, clk+ should be driven directly from a cmos gate, and the clk? pin should be bypassed to ground with a 0.1 f c a pacitor in parallel with a 39 k? resistor (see figure 46 ). although the clk+ input circuit supply is avdd (1.8 v), this input is de signed to withstand input voltages of up to 3.3 v and , therefore , offers several sele c tions for the drive logic voltage. 0.1f 0.1f 0.1f 39 k? 50 ?* 0.1f clk clk clk? clk+ adc ad9639 cmos driver clk+ ad9510/ad9511/ ad9512/ad9513/ ad9514/ad9515/ ad9516/ad9518 *50? resistor is optional. optional 100? 07973-021 figure 46 . single - ended 1.8 v cmos sample clock 0.1f 0.1f 0.1f clk clk 0.1f clk? clk+ adc ad9639 optional 100? cmos driver clk+ ad9510/ad9511/ ad9512/ad9513/ ad9514/ad9515/ ad9516/ad9518 *50? resistor is optional. 50 ?* 07973-022 figure 47 . single - ended 3.3 v cm os sample clock clock duty cycle considerations typical high speed adcs use both clock edges to generate a variety of internal timing signals. as a result, these adcs may be sens i tive to the clock duty cycle. commonly, a 5% tolerance is required on the clo ck duty cycle to maintain dynamic perfor - mance characteristics. the ad9639 contains a duty cycle stabilizer (dcs) that retimes the nonsampling edge, providing an internal clock signal with a nom i nal 50% duty cycle. this allows a wide range of clock input duty cycles without affecting the performance of the ad9639 . when the dcs is on (default) , noise and distortion perfor mance are nearly flat for a wide range of duty c y cles. however, some applications may require the dcs function to be off. if so, keep in m ind that the dynamic range performance may be affected when operated in this mode. see the memory map section for more details on using this feature. jitter in the rising edge of the input is an important concern, and it is not reduced by the internal stabilization circuit. the duty cycle control loop does not functio n for clock rates of less than 50 mhz nominal. it is not recommended that this adc clock be dynamic in nature. moving the clock around dynami - cally req uire s long wait times for th e back end serial capture to retime and re synchronize to the receiving logic. this long time con s tant far exceeds the time that it takes for the d cs and the pll to lock and stabilize. only in rare applications would it be necess ary to disable the dcs circuitry in the clock r egi ster (see address 0x09 in table 15) . keeping the dcs circuit enabled is recommended to maximize ac performance.
ad9639 data sheet rev. b | page 20 of 36 clock jitter considerations high speed, high resolut ion adcs are sensitive to the quality of the clock input. the degradation in snr at a given input frequency ( f a ) due only to aperture jitter ( t j ) can be calc u lated as follows: snr degradation = 20 log 10(1/2 f a t j ) in this equation, the rms apert ure jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and adc aperture jitter. if undersampling applications are particularly sensitive to jitter (see figure 48 ). the clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the ad9639 . power supplies for clock drivers should be separated from the adc output driver supplies to avoid modulating the clock signal with digital noise. low jitter, crystal - controlled oscillators are the best clock sources. if the clock is generated from another type of source (by gating, dividing, or another met h od), it should be retimed by the original clock during the last step. refer to the an - 501 application note , the an - 756 application note , and the analog dialogue article , analog - to - digital converter clock optimization: a test engineering perspective (volume 42, number 2, february 2008) for in - depth information about jitter performan ce as it relates to adcs (visit www.analog.com ). 1 10 100 1000 30 40 50 60 70 80 90 100 110 120 130 0.125 ps 0.25 ps 0.5 ps 1.0 ps 2.0 ps rms clock jitter requirement snr (db) 07973-024 analog input frequency (mhz) 16 bits 14 bits 12 bits 10 bits figure 48 . ideal snr vs. input frequency and jitter power dissipation as shown in figure 49 and figure 50 , the power dissipated by the ad9639 is proportional to its clock rate . the digital power dissipation does not vary significantly because it is determined primarily by the drvdd supply and the bias current of the digital output drivers. 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 50 90 70 110 130 150 170 encode (msps) power (w) current (ma) i a vdd power i dr vdd 07973-056 figure 49 . supply current vs. encode for f in = 84.3 mhz, f sample = 170 msps 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 50 9070 110 130 150 170 190 210 encode (msps) power (w) current (ma) i a vdd power i dr vdd 07973-057 figure 50 . supply current vs. encode for f in = 84.3 mhz, f sample = 210 msps
data sheet ad9639 rev. b | page 21 of 36 digital outputs serial data frame the ad9639 digi tal output complies with the jedec s tandard no. 204 (jesd204), which describes a serial interface for data converters. jesd204 uses 8b/10b encoding as well as optional scrambling. k28.5 and k28.7 comma symbols are used for frame synchronization. the receiver is required to lock onto the serial data stream and recover the clock with the use of a pll. (refer to ie e e std 802.3 - 2002, section 3 , for a complete 8b/10b and comma symbol description.) the 8b/10b encoding works by taking eight bits of data (an octet) and encoding them into a 10 - bit symbol . in the ad9639, the 12 - bit converter word is broken into two octets. bit 11 through bit 4 are in the first octet. the second octet contains bit 3 through bit 0 and four tail bits. the msb of the tail bits can also be used to indicate an out - of -r ange condition. the tail bits are configured using the jesd204 r egister , address 0x033[3]. t he two resulting octets are optionally scrambled and encoded into their corresponding 10 - bit code. the scrambling function is controll ed by the jesd204 register, address 0x033[0]. figure 51 shows how the 12 - bit data is taken from the adc, the tail bits are added, the two octets are scrambled , and the octets are encoded into two 10 - bit symbols. figure 52 illustrates the data format. the scrambler uses a self - synchronizing polynomial - based algorithm defined by the equation 1 + x 14 + x 15 . the descrambler in the receiver should be a self - synchronizing version of the scrambler polynomial. a 16 - bit parallel implementation is shown in figure 54. refer to jedec standard no. 204 - april 2006 , s ection 5.1 , for complete transport layer and data format details and s ection 5.2 for a complete expl anation of scrambling and descrambling . 07973-201 data from adc frame assembler (add tail bits) scrambler 1 + x 14 + x 15 8b/10b encoder to receiver figure 51 . adc data output path 07973-200 word 0[11:4] symbol 0[9:0] word 0[3:0],tail bits[3:0] symbol 1[9:0] word 1[11:4] symbol 2[9:0] word 1[3:0], tail bits[3:0] symbol 3[9:0] time frame 0 frame 1 figure 52 . 12- bit data transmission with tail bits 07973-202 8b/10b decoder descrambler 1 + x 14 + x 15 frame alignment data out from transmitter figure 53 . required receiver data path
ad9639 data sheet rev. b | page 22 of 36 d30 s30 d q clk s14 d31 s31 d q clk s15 d29 s29 d q clk s13 s15 d28 s28 d q clk s12 s14 d27 s27 d q clk s11 s13 d26 s26 d q clk s10 s12 d25 s25 d q clk s9 s11 d24 s24 d q clk s8 s10 d23 s23 d q clk s7 s9 d22 s22 d q clk s6 s8 d21 s21 d q clk s5 s7 d20 s20 d q clk s4 s6 d19 s19 d q clk s3 s5 d18 s18 d q clk s2 s4 d17 s17 d q clk s1 s3 d16 s16 s1 s2 clk = frame clk first octet of frame lsb msb second octet of frame lsb msb lsb msb 07973-203 fig ure 54 . parallel descrambler required in receiver
data sheet ad9639 rev. b | page 23 of 36 initial synchronization the serial interface must synchronize to the frame boundaries before data can be properly decoded. the jesd204 standard has a synchronization routine to i dentify the frame boundary. t he pgmx pins are used as sync pin s by default. when the sync pin is taken low for at least two clock cycles, the ad9639 enters the synchronization mode. the ad9639 transmit s the k28 .5 comma symbol until the receiver can identify the frame boundar y. the receiver should then deassert the sync signal (take sync high) and the adc begin s transmitting real data. the first non - k28.5 symbol is the msb symbol of the 12 - bit data. to minimize skew and time misalignment between each channel of the digital outputs, the following actions should be taken to ensure that each channel data frame is within 1 clock cycle of the sample clock. for some receiver logic, this is not r equired. 1. full power - down through external pdwn pin. 2. chip reset via external reset pin. 3. power - up by releasing external pdwn pin. init reset kcounter < 4 kcounter = 4 vcounter = 4 vcounter < 4 and icounter < 3 icounter = 3 sync_request = ?0?; kcounter = ?0?; if /invalid/ then icounter = icounter + ?1?; vcounter = ?0?; else if /valid/ then vcounter = vcounter + ?1?; end if; check data /valid/ /invalid/ icounter = ?0?; vcounter = ?0?; icounter = ?0?; vcounter = ?0?; sync_request = ?1?; if /k28.5/ and /valid/ then kcounter = kcounter + ?1?; else kcounter = ?0?; end if; 07973-204 figure 55 . receiver state machine table 8 . variables used in receiver sta te machine variable description i counter counter used in the check phase to count the number of invalid symbols . /invalid/ asserted by receiver to indicate that the current symbol is an invalid symbol given the current running disparity . /k28.5/ asserte d when the current symbol corresponds to the k28.5 control character . k counter counter used in the init phase to count the number of valid k28.5 symbols . sync _request asserted by receiver when loss of code group synchronization is detected . /valid/ asse rted by receiver to indicate that the c urrent symbol is a valid symbol given the current running disparity . v counter counter used in the check phase to count the number of successive valid symbols .
ad9639 data sheet rev. b | page 24 of 36 continuous synchronization continuous sync hronizati on is part of the jesd204 specification. the 12 - bit word requires two octets to transmit all the data. the two octets (msb and lsb) are called a frame. when scrambling is disabled and the lsb octets of two consecutive frames are the same, the second lsb oc tet is replaced by a k28.7 comma symbol. the receiver is responsible for replacing the k28.7 comma symbol with the lsb octet of the previous frame . when scrambling is enabled, any d28.7 symbols found in the lsb octet of a frame are replaced with k28.7 comm a symbols. the receiver is responsible for replacing the k28.7 comma symbols with d28.7 symbols when in this mode. by looking for k28.7 symbols, the receiver ca n e nsure that it is still synchronized to the frame boundary. 07973-205 if /k28.7/ /replace_k28.7/ if (ocounter == previous_position) and /valid/ /reset_octet_counter/ end if; if /valid/ | (ocounter == n-1) previous_position = ocounter end if; end if; figure 56 . pseudocode for data dependent frame synchronization in receiver table 9 . variables and functions in data dependent frame synchronization variable description n number of octets in frame (octet indexing starts from 0) . /k28 .7/ asserted when the current symbol corresponds to the k28.7 control character. o counter counter used to mark the position of the current octet in the frame . previous _ position variable that stores the position in the frame of a k28.7 symbol . /replace_k 28.7/ replace k28.7 at the decoder output as follows. w hen scrambling is disabled, replace k28.7 with the lsb octet that was decoded at the same position in the previous frame ; when scrambling is enabled, replace k28.7 at the decoder output with d28.7. /r eset_octet_counter/ reset octet counter to 0 at reception of next octet . /valid/ asserted by receiver to indicate that the current symbol is a valid symbol given the current running disparity .
data sheet ad9639 rev. b | page 25 of 36 digital outputs and timing the ad9639 has differential digital outputs that power up by default. the driver current is derived on chip and sets the output current at each output equal to a nominal 4 ma. each output presents a 100 dynamic internal termination to reduce unwanted reflections. a 100 differential termination resistor should be placed at each receiver input to result in a nominal 400 mv peak-to-peak swing at the receiver. alternatively, single-ended 50 termina- tion can be used. when single-ended termination is used, the termination voltage should be drvdd/2; otherwise, ac coupling capacitors can be used to terminate to any single-ended voltage. the ad9639 digital outputs can interface with custom asics and fpga receivers, providing superior switching performance in noisy environments. single point-to-point network topologies are recommended with a single differential 100 termination resistor placed as close to the receiver logic as possible. the common mode of the digital output automatically biases itself to half the supply of drvdd if dc-coupled connecting is used. for receiver logic that is not within the bounds of the drvdd supply, an ac-coupled connection should be used. simply place a 0.1 f capacitor on each output pin and derive a 100 differential termination close to the receiver side. if there is no far-end receiver termination or if there is poor differential trace routing, timing errors may result. to avoid such timing errors, it is recommended that the trace length be less than 6 inches and that the differential output traces be close together and at equal lengths. 100 ? 100 ? differential trace pair dout + x drvdd dout ? x v cm = drvdd/2 output swing = 400mv p-p receiver 07973-092 figure 57. dc-coupled digital output termination example 100 ? or 100 ? differential trace pair dout + x drvdd v rxcm dout ? x v cm = rx v cm output swing = 400mv p-p 0.1f 0.1f receiver 07973-093 figure 58. ac-coupled digital output termination example
ad9639 data sheet rev. b | page 26 of 36 ?200 ?100 0 100 200 ?30 ?10 0 10 30 ?0.5 0.5 time (ps) time (ps) uls 400 600 200 0 ?200 ?400 ?600 voltage (mv) height1: eye diagram tie1: histogram tj@beri: bathtub 1 + 500 600 400 300 200 100 0 hits 10 0 10 ?2 10 ?4 10 ?6 10 ?8 10 ?10 10 ?12 10 ?14 ber 3 + 2 + eye: all bits offset: 0.015 uls: 5000: 40044, total: 12000: 80091 (y1) (y2) ( ? y) ?375.023m +409.847m +784.671m 07973-094 figure 59. digital outputs data eye with tr ace lengths less than 6 inches on standard fr-4, external 100 terminations at rece iver ?200 ?100 0 100 200 ?50 0 50 time (ps) time (ps) 400 600 200 0 ?200 ?400 ?600 vol t age (mv) 250 300 200 150 100 50 0 hits height1: eye diagram tie1: histogram 0 ?0.5 0.5 uls ber tj@beri: b a thtub 3 + 2 + 1 + (y1) (y2) ( ? y) ?402.016m +398.373m +800.389m eye: all bits offset: 0.015 uls: 5000: 40044, total 8000: 40044 0 7973-095 10 0 10 ?2 10 ?4 10 ?6 10 ?8 10 ?10 10 ?12 10 ?14 figure 60. digital outputs data eye with trace lengths greater than 12 inches on standard fr-4, external 100 terminations at receiver figure 59 shows an example of the digital output (default) data eye and a time interval error (tie) jitter histogram with trace lengths less than 6 inches on standard fr-4 material. figure 60 shows an example of trace lengths exceeding 12 inches on stan- dard fr-4 material. note that the tie jitter histogram reflects the decrease of the data eye opening as the edge deviates from the ideal position. it is the users responsibility to determine whether the waveforms meet the timing budget of the design when the trace lengths exceed 6 inches. additional spi options allow the user to further increase the output driver voltage swing of all four outputs to drive longer trace lengths (see address 0x15 in table 15). even though this produces sharper rise and fall times on the data edges and is less prone to bit errors, the power dissipation of the drvdd supply increases when this option is used. see the memory map section for more details. the format of the output data is offset binary by default. table 10 provides an example of this output coding format. to change the output data format to twos complement or gray code, see the memory map section (address 0x14 in table 15). table 10. digital output coding code (vin + x) ? (vin ? x), input span = 1.25 v p-p (v) digital output offset binary ([d11:d0]) 4095 +0.625 1111 1111 1111 2048 0.00 1000 0000 0000 2047 ?0.000305 0111 1111 1111 0 ?0.625 0000 0000 0000 the lowest typical clock rate is 100 msps. for clock rates slower than 100 msps, the user can set bit 3 to 0 in the serial control register (address 0x21 in table 15). this option allows the user to adjust the pll loop bandwidth to use clock rates as low as 50 msps.
data sheet ad9639 rev. b | page 27 of 36 setting bit 2 in t he output mode r egister (address 0x 14 ) allows the user to invert the digital outputs from their nominal state. this is not to be confused with inverting the serial stream to an lsb first mode. in default mode, as shown in f igure 2 , the msb is first in the data output serial stream. however, this order can be inverted so that the lsb is first in the data output serial stream . there are eight digital output test pattern options available that can be initiated through the spi (see table 12 for the output bit sequencing options ). this feature is useful when validating receiver capture and timing. some test patterns have two serial sequential words and can be alternated in various ways, depending on the test pattern selected . note that some patterns do not adhere to the data format select option. in addition, c ustom user - defined test patterns can be assigned in the user pattern registers (address 0x19 through address 0x20 ). the pn sequence short pattern p roduces a pseudorandom bit sequence that repeats itself every 2 9 ? 1 ( 511 ) bits. a description of the pn sequence short and how it is generated can be found in section 5.1 of the itu - t o .150 (05/96) recommendation. the only difference is that the starting value must be a specific value instead of all 1s (see table 11 for the initial values). the pn sequence long pattern produces a pseudorandom bit sequence that repeats itself every 2 23 ? 1 ( 8,388,607 ) bits. a description of the pn sequence long and how it is generated can be fo und in section 5.6 of the itu - t o .150 (05/96) standard. the only differences are that the starting value must be a specific value instead of all 1s ( see table 11 for the initial values) and th at th e ad9639 inverts the bit stream with relation to the itu -t standard. table 11 . pn sequence sequence initial value first three output samples (msb first) pn sequence short 0x0df 0x df 9, 0x353, 0x301 pn sequence long 0x29b80a 0x591, 0x fd 7, 0x0 a3 consult the memory map section for information on how to change these additional digital output timing features through the spi. table 12 . flexible output test modes output test mode bit sequence patter n name digital output word 1 digital output word 2 subject to data format select 0000 off (default) n/a n/a yes 0001 midscale short 1000 0000 0000 same yes 0010 +full - scale short 1111 1111 1111 same yes 0011 ?full - scale short 0000 0000 0000 same yes 0100 checkerboard 1010 1010 1010 0101 0101 0101 no 0101 pn sequence long 1 n/a n/a yes 0110 pn sequence short 1 n/a n/a yes 0111 one - /zero - word toggle 1111 1111 1111 0000 0000 0000 no 1 all test mode options except pn sequence long and pn sequence short can support 8 - to 14 - bit word lengths to verify data capture to the receiver.
ad9639 data sheet rev. b | page 28 of 36 tempout pin the tempout pin can be used as a coarse temperature sensor to monitor the internal die temperature of the device. this pin typically has a 737 mv output with a clock rate of 210 msps and a negative going temperature coefficient of ?1.12 mv/c. the voltage response of this pin is characterized in figure 61. 0.85 0.83 0.81 0.79 0.77 0.75 0.73 0.71 0.69 0.67 0.65 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 temperature (c) tempout pin voltage (v) 07973-055 figure 61. tempout pin voltage vs. temperature rbias pin to set the internal core bias current of the adc, place a resistor (nominally equal to 10.0 k) between ground and the rbias pin. the resistor current is derived on chip and sets the avdd current of the adc to a nominal 610 ma at 210 msps. therefore, it is imperative that a 1% or less tolerance on this resistor be used to achieve consistent performance. vcm x pins the common-mode output pins can be enabled through the spi to provide an external reference bias voltage of 1.4 v for driving the vin + x/vin ? x analog inputs. the vcm x pins may be required when connecting external devices, such as an amplifier or transformer, to interface to the analog inputs. reset pin the reset pin resets the datapath and sets all spi registers to their default values. to use this pin, the user must resynchronize the digital outputs. this pin is only 1.8 v tolerant. pdwn pin when asserted high, the pdwn pin turns off all adc channels, including the output drivers. this function can be changed to a standby function (see address 0x08 in table 15). this feature allows the user to place all channels into standby mode. the output drivers transmit pseudorandom data until the outputs are disabled using the output mode register (address 0x14). when the pdwn pin is asserted high, the ad9639 is placed into power-down mode, shutting down the reference, reference buffer, pll, and biasing networks. in this state, the adc typically dissipates 3 mw. if any of the spi features are changed before the power-down feature is enabled, the chip continues to function after pdwn is pulled low without requiring a reset. the ad9639 returns to normal operating mode when the pdwn pin is pulled low. this pin is only 1.8 v tolerant. sdo pin the sdo pin is for use in applications that require a 4-wire spi mode operation. for normal operation, it should be tied low to agnd through a 10 k resistor. alternatively, the device pin can be left open, and the 345 internal pull-down resistor pulls this pin low. this pin is only 1.8 v tolerant. sdi/sdio pin the sdi/sdio pin is for use in applications that require either a 4- or 3-wire spi mode operation. for normal operation, it should be tied low to agnd through a 10 k resistor. alternatively, the device pin can be left open, and the 30 k internal pull- down resistor pulls this pin low. this pin is only 1.8 v tolerant. sclk pin for normal operation, the sclk pin should be tied to agnd through a 10 k resistor. alternatively, the device pin can be left open, and the 30 k internal pull-down resistor pulls this pin low. this pin is only 1.8 v tolerant. csb pin for normal operation, the csb pin should be tied high to avdd through a 10 k resistor. alternatively, the device pin can be left open, and the 26 k internal pull-up resistor pulls this pin high. tying the csb pin to avdd causes all information on the sclk and sdi/sdio pins to be ignored. tying the csb pin low causes all information on the sdo and sdi/sdio pins to be written to the device. this feature allows the user to reduce the number of traces to the device if necessary. this pin is only 1.8 v tolerant. pgmx pins all pgmx pins are automatically initialized as synchronization pins by default. these pins are used to lock the fpga timing and data capture during initial startup. these pins are respective to each channel (pgm3 = channel a, pgm2 = channel b, and so on). the sync (pgmx) pin should be pulled high until this pin receives a low signal input from the receiver, during which time the adc outputs k28.5 comma symbols to indicate the frame boundary. when the receiver finds the frame boundary, the sync identification is deasserted low and the adc outputs the valid data on the next packet boundary. when steady state operation for the device is achieved, these pins can be assigned as a standby option using the pgm mode register (address 0x53 in table 15). all other pgmx pins become global synchronization pins. this pin is only 1.8 v tolerant.
data sheet ad9639 rev. b | page 29 of 36 serial port interface (spi) the ad9639 serial port interface allows the user to configure the converter for specific functions or operations through a struc tured register space provided in the adc. the spi can provide the user with additional flexibility and customization, depending on the application. addresses are accessed via the serial port and can be written to or read from via the port. memory is organi zed into bytes that can be further divided into fields, as documented in the memory map section. detailed operational information can be found in the analog devices, inc., an - 877 application note, interfacing to high speed adcs vi a spi . four pins define the spi: sclk, sdi/sdio , sdo, and csb (see table 13 ). the sclk pin is used to synchronize the read and write data presented to the adc. the sdi/sdio pin is a dual - purpose pin that allows data to be sen t to and read from the internal adc memory map registers. the sdo pin is used in 4- wire mode to read back data from the part. the csb pin is an active low control that enables or disables the read and write cycles. table 13 . serial port pins pin function sclk s erial clock. s erial shift clock input. sclk is used to synchronize serial interface reads and writes. sdi/sdio serial d ata i nput/ o utput. d ual - purpose pin that typical ly serves as an input or an output, depending on the spi w ire mode , the instruction sent , and the relative position in the timing frame. sdo serial data output. u sed only in 4 - wire spi mode. when se t, the sdo pin becomes active. when clear ed , the sdo pin remains in three - state and all read data is routed to the sdi/sdio pin. csb chip s elect b ar ( a ctive l ow). this control gates the read and write cycles. the falling edge of csb in conjunction with the rising edge of sclk determine s the start of the framing sequence. during the instruction phase, a 16 - bit instru ction is transmitted , followed by one or more data bytes, which is determined by bit field w0 and bit field w1. an example of the serial timing and its defini - tions can be found in figure 63 and tab le 14 . during normal operation, csb is used to signal to the device that spi commands are to be received and processed. when csb is brought low, the device processes sclk and sdi/sdio to execute instructions. normally, csb remains low until the communicat ion cycle is complete. however, if connected to a slow device, csb can be brought high between bytes, allowing older microcontrollers enough time to transfer data into shift registers. csb can be stalled when transferring one, two, or three bytes of data. when w0 and w1 are set to 11, the device enters streaming mode and continues to process data, either reading or writing, until csb is taken high to end the communication cycle. this allows complete memory transfers without requiring additional instructio ns. regardless of the mode, if csb is taken high in the middle of a byte transfer, the spi state machine is reset and the device waits for a new instruction. in addition to the operation modes, the spi port configuration influences how the ad9639 operates. for applications that do not require a control port, the csb line can be tied high. this places the sdi/sdio pin into its secondary mode , as defined in the sdi/sdio pin section . csb can also be tied low to enable 2- wire mode. when csb is tied low, sclk and sdi/sdio are the only pins required for communication. although the device is synchronized during power - up, the user should ensure that the serial port remains synchronized with the csb line when using this mode . when operating in 2 - wire mode, it is recom - mended that a 1 - , 2 - , or 3 - byte transfer be used exclusively. without an active csb line, streaming mode can be entered but not exited. in addition to word length, the instruction phase determines whether the se rial frame is a read or write operation, allowing the serial port to be used to both program the chip and read the contents of the on - chip memory. if the instruction is a readback operation, performing a readback causes the sdi/sdio pin to change from an i nput to an output at the appropriate point in the serial frame. dat a can be sent in msb first or lsb first mode. msb first mode is the default at power - up and can be changed by adjusting the configuration register (address 0x00) . for more information about this and other features, see the an - 877 application note, interfacing to high speed adcs via spi . hardware interface the pins described in table 13 constitute the physical interface between the users programming device and t he serial port of the ad9639 . the sclk and csb pins function as inputs when using the spi. the sdi/ sdio pin is bidirectional, functioning as an input during write phases and as an output during readback. if multiple sdi/sdio pins share a common connection, ensure that proper v oh levels are met. assuming the same load for each ad9639 , figure 62 shows the number of sdi/sdio pins that can be connected together and the resulting v oh level. this interface is flexible enough to be co ntrolled by either serial prom s or pic mi c rocontrollers, providing the user with an alternative method, other than a full spi controller, to program the adc (see the an - 812 application note ). for users who wish to operate the adc with out using the spi, remove any connections from the csb , sclk, sd o , and sdi/sdio pins. by disconnecting these pins from the control bus, the adc can function in its most basic operation. each of these pins has an internal termination that floats to its res pective level.
ad9639 data sheet rev. b | page 30 of 36 number of sdi/sdio pins connected together v oh (v) 1.715 1.720 1.725 1.730 1.735 1.740 1.745 1.750 1.755 1.760 1.765 1.770 1.775 1.780 1.785 1.790 1.795 1.800 03 0 2010 40 50 60 70 80 90 100 07973-104 figure 62. sdi/sdio pin loading don?t care don?t care don?t care don?t care sdi/ sdio sclk t s t dh t high t clk t low t ds t h r/w w1w0a12a11a10a9a8a7 d5d4d3d2d1d0 csb 07973-028 figure 63. serial timing details table 14. serial timing definitions parameter timing (ns min) description t ds 5 setup time between the data and the rising edge of sclk t dh 2 hold time between the data and the rising edge of sclk t clk 40 period of the clock t s 5 setup time between csb and sclk t h 2 hold time between csb and sclk t high 16 minimum period that sclk should be in a logic high state t low 16 minimum period that sclk should be in a logic low state t en_sdi/sdio 10 minimum time for the sdi/sdio pin to switch fr om an input to an output relative to the sclk falling edge (not shown in figure 63) t dis_sdi/sdio 10 minimum time for the sdi/sdio pin to switch fr om an output to an in put relative to the sclk rising edge (not shown in figure 63)
data sheet ad9639 rev. b | page 31 of 36 memory map reading the memory m ap table each row in the memory map register table ( table 15 ) has eight bit locations. the memory map is divided into three sections: the chip configuration register s (address 0x00 to address 0x02), the device index and transfer reg ister s (address 0x05 and addr ess 0xff), and the adc function register s (address 0x08 to address 0x 53 ). the leftmost column of the memory map indicates the register address ; the default value is shown in the second rightmost column. the bit 7 column is the start of the default hexadecimal value given. for example, address 0x09, the clock register, has a default value of 0x01, meaning that bit 7 = 0, bit 6 = 0, bit 5 = 0, bit 4 = 0, bit 3 = 0, bit 2 = 0, bit 1 = 0, and bit 0 = 1, or 0000 0001 in binary. this setting is the default for the duty cycle stabilizer in the on condition. by writing a 0 to bit 0 of this address , fol - lowed by 0x01 in the device update register (address 0xff[0], the transfer bit), the duty cycle stabilizer is turn ed off. it is importan t to follow each writ e sequence with a transfer bit to update the spi registers. for more information about this and other functions, consult the an - 877 application note, interfacing to high speed adcs via spi . reserved locations undefined memory location s should not be written to except when writing the default values suggested in this data sheet. blank cells in table 15 should be considered reserved bits and have a 0 written into their registers during power - up. default values w hen the ad9639 comes out of a reset, critical registers are preloaded with default values. these values are indicated in table 15 . logic levels in table 15 , bit is set is synonymous with bit is set to logic 1 or writing logic 1 for the bit. similarly, bit is cleared is synon - ymous with bit is set to logic 0 or writing logic 0 for the bit.
ad9639 data sheet rev. b | page 32 of 36 table 15. memory map register addr. (hex) register name (msb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 (lsb) bit 0 default value (hex) comments chip configuration registers 0 x0 0 chip_port_ config (local, master) sdo active (not require d, ignored if not used) lsb first soft reset 16- bit address (default mode for adcs) 0x18 0 x0 1 chip_id (global) 8- bit c hip id , bits[2:0] 0x29 : ad9639 , 12- bit quad read only . 0 x0 2 chip_grade (global) speed grade 010 = 170 msps 100 = 210 msps read only . device index and transfer registers 0 x0 5 device_ index_a (global) adc a adc b adc c adc d 0x0f bits are set to determine which device on chip receives the next write command. the default is all devices on chip. 0x ff device_ update (local, master) sw transfer 1 = on 0 = off (default) 0x00 synchro - nously transfers data from the master shift register to the slave. adc function registers 0 x0 8 modes (local) external pdwn pin function 00 = f ull power -down (default) 01 = standby power- down mode 00 = chip run (default) 01 = full power - down 10 = standby 11 = reset 0x00 determines ge n eric modes of chip operation. 0 x0 9 clock (global) duty cycle stabilize 1 = on (default) 0 = o ff 0x01 turns the internal duty cycle stabilizer on and off. 0 x0 d test_io (local ) reset pn sequence long gen 1 = on 0 = off (default) reset pn sequence short gen 1 = on 0 = off (default) flexible output test mode 0000 = off (normal operation) 0001 = midscale short 0010 = +fs short 0011 = ?fs short 0100 = checker board output 0101 = pn 23 sequence 0110 = pn 9 sequence 0111 = 1/0 word toggle 0x00 when set, the test data is placed on the output pins in place of nor mal data. 0 x0 e test_bist (local) bist init 1 = on 0 = off (default) bist enable 1 = on 0 = off (default) 0x00 when bit 0 is set, the built - in self - test function is initiated. 0x0f adc_in put (local) analog disconnect enable 1 = on 0 = off (default) vcm enable 1 = on 0 = off (default) 0x00
data sheet ad9639 rev. b | page 33 of 36 addr. (hex) register name (msb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 (lsb) bit 0 default value (hex) comments 0x10 o ffset (local) 6- bit d evice o ffset a djustment[5:0] 011111 = +31 lsb 011110 = +30 lsb 011101 = +29 lsb 000010 = +2 lsb 000001 = +1 l sb 000000 = 0 lsb 111111 = ?1 lsb 111110 = ?2 lsb 111101 = ?3 lsb 100001 = ?31 lsb 100000 = ?32 lsb 0x 00 device offset trim. 0x14 output_mode (local/global) output enable bar (local) 1 = off 0 = on (default) output invert enable (global) 1 = on 0 = off (default) data format select (global) 0 0 = offset binary (default) 01 = twos complement 10 = gray code 0x00 configures the outputs and the format of the data. 0x15 output_adjust (global) output d rive r c urrent[1:0] 00 = 400 mv (default) 01 = 500 mv 10 = 440 mv 11 = 320 mv 0x00 vcm output adjustments. 0x18 v ref (global) ref_vfs[4:0] reference full - scale adj ust 10000 = 0.98 v p -p 10001 = 1.00 v p -p 10010 = 1. 02 v p -p 10011 = 1. 04 v p -p 11111 = 1. 23 v p -p 00000 = 1. 25 v p -p 00001 = 1. 27 v p -p 01110 = 1. 48 v p -p 01111 = 1.5 v p -p 0x00 select adjustments for v ref . 0x19 user_ patt1_lsb (local) b7 b6 b5 b4 b3 b2 b1 b0 0x aa user -d efined pattern 1 lsb. 0x1a user_ patt1_msb (local) b15 b14 b13 b12 b11 b10 b9 b8 0x aa user - defined pattern 1 m sb. 0x1b user_ patt2_lsb (local) b7 b6 b5 b4 b3 b2 b1 b0 0x aa user - defined pattern 2 lsb . 0x1c user_ patt2_msb (local) b15 b14 b13 b12 b11 b10 b9 b8 0x aa user - defined pattern 2 msb . 0x1d user_ patt3_lsb (local) b7 b6 b5 b4 b3 b2 b1 b0 0x aa user - defined pattern 3 lsb. 0x1e user_ patt3_msb (local) b15 b14 b13 b12 b11 b10 b9 b8 0x aa user - defined pattern 3 msb . 0x1f user_ patt4_lsb (local) b7 b6 b5 b4 b3 b2 b1 b0 0x aa user - defined pattern 4 lsb. 0x20 user_ patt4_msb (local) b15 b14 b13 b12 b11 b10 b9 b8 0xcc user - defined pattern 4 msb .
ad9639 data sheet rev. b | page 34 of 36 addr. (hex) register name (msb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 (lsb) bit 0 default value (hex) comments 0x21 serial_control (global) pll high encode rate mode (global) 0 = low rate 1 = high rate (default) 0x08 serial stream control. 0x24 misr_lsb (local) b7 b6 b5 b4 b3 b2 b1 b0 0x00 least significant byte of misr. read only. 0x25 misr_msb (local) b15 b14 b13 b12 b11 b10 b9 b8 0x00 most significant byte of misr. read only. 0x33 jesd204 ( global ) over- range in lsb of tail bits 0 = over - range disabled (default) 1 = over - range enabled scram - bling enable 0 = scram - bling disabled (default) 1 = scram - bling enabled 0x00 0x50 coarse_ gain_adj (local) gain adjust enable 1 = on 0 = off (default) coarse gain a djust[5:0] = o utput[63:0] 000000 = 00000001 000001 = 00000011 000010 = 00000111 111101 = 00111111 111110 = 01111111 111111 = 11111111 0x00 0x51 fine_ gain_adj (local) fine g ain a djust[3:0] = o utput[15:0] 0000 = 0000000000000001 0001 = 0000000000000010 0010 = 0000000000000100 1101 = 0010000000000000 1110 = 0100000000000000 1111 = 1000000000000000 0x00 0x52 gain_cal_ctl temperature sensor enable 1 = on 0 = off (default) gain quarter lsb 1 = on 0 = o ff (default) gain cal resetb 1 = on (default) 0 = off gain cal enable 1 = on 0 = off (default) 0x02 0x53 dynamic pgm pins (global) pgm_3 00 = sync 01 = s tandby a 10 = s tandby a and standby d 11 = s tandby a and standby b pgm_2 00 = sync 01 = s tandby b 10 = s tandby b and standby c 11 = s tandby b and standby a pgm_1 00 = sync 01 = standby c 10 = standby c and standby b 11 = standby c and standby d pgm_0 00 = sync 01 = standby d 10 = standby d and standby a 11 = standby d and standby c 0x00 standby = adc core off, pn23 enabled, serial channel enabled.
data sheet ad9639 rev. b | page 35 of 36 applications informa tion power and ground recommendations when connecting power to the ad9639 , it is recommended that two separate 1.8 v supplies be used: one for analog (avdd) and one for digital (d rvdd). if only one supply is available, it should be routed to the avdd pin first and then tapped off and isolated with a ferrite bead or a filter choke preceded by decou - pling capacitors for the drvdd pin . s everal different decoupling capacitors can be us ed to cover both high and low frequencies. locate t hese capacitors close to the point of entry at the pc b level and close to the parts, with minimal trace lengths. a single pc b ground plane should be sufficient when using the ad9639 . with proper decoupling a nd smart parti tioning of the analog, digital, and clock sections of the pcb , optimum perfor - mance can easily be achieved. exposed paddle therm al heat slug recommendations it is required that the exposed paddle on the underside of the adc be connected to analog ground (agnd) to achieve the best electrical and thermal performance of the ad9639 . an exposed continuous copper plane on the pcb should mate to the ad9639 exposed paddle, pin 0. the copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the pcb. these vias should be solder - filled or plugged with non conductive epoxy . to maximize the coverage and adhesion between the adc and pcb, partition the continuous copper p lane into several uniform sections by overlaying a silkscreen on the pcb. this provides several tie points between the adc and pcb during the reflow process, whereas using one continuous plane with no partitions guarantees only one tie point. see figure 64 for a pcb layout example. for detailed information on packaging and the pcb layout of chip scale packages, see the an - 772 ap plication note , a design and manufacturing guide for the lead frame chip scale package (lfcsp) , at www.analog.com . silkscreen p artition pin 1 indic at or 07973-029 figure 64 . typical pcb layout
ad9639 data sheet rev. b | page 36 of 36 outline dimensions compliant to jedec standards mo-220-vnnd-4 0.20 ref 0.80 max 0.65 ty p 1.00 0.85 0.80 0.05 max 0.02 nom 1 18 54 37 19 36 72 55 0.50 0.40 0.30 8.50 ref pin 1 indic at or sea ting plane 12 max 0.60 0.42 0.24 0.60 0.42 0.24 0.30 0.23 0.18 0.50 bsc pin 1 indic at or coplanarit y 0.08 06-25-2012- a for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. top view exposed p ad bot t om view 10.10 10.00 sq 9.90 9.85 9.75 sq 9.65 0.25 min 8.35 8.20 sq 8.05 figure 65 . 72 -l ead lead frame chip scale package [ lfcsp _vq ] 10 mm 10 mm body, very thin quad (cp - 72 -3 ) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ad9639 bcpz -170 ?40 c to +85c 72-le ad lead frame chip scale package [ lf csp _vq] cp-72-3 ad9639 bcpz rl -170 ?40 c to +85c 72- lead lead frame chip scale package [lfcsp _vq] cp-72-3 ad9639 bcpz -210 ?40 c to +85c 72- lead lead frame chip scale package [lfcsp _vq] cp-72-3 ad9639 bcpz rl -210 ?40 c to +85c 72- lead lead frame chip scale package [lfcsp _vq] cp-72-3 ad9639-21 0kitz evaluation board 1 z = rohs compliant part. ? 2009 C 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d07973 -0- 7 /13(b)

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